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課程名稱 |
積體電路設計自動化
VLSI DESIGN AUTOMATION |
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開課學期 |
96-2 |
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授課對象 |
電機資訊學院 電機工程學研究所 |
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授課教師 |
李建模 |
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課號 |
EEE5020 |
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課程識別碼 |
943 U0220 |
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班次 |
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學分 |
3 |
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全/半年 |
半年 |
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必/選修 |
選修 |
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上課時間 |
星期五2,3,4(9:10~12:10) |
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上課地點 |
電二229 |
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備註 |
總人數上限：60人 |
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Ceiba 課程網頁 |
http://ceiba.ntu.edu.tw/962_vlsida |
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課程簡介影片 |
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核心能力關聯 |
核心能力與課程規劃關聯圖 |
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課程大綱
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課程概述 |
This course focuses on the underlying techniques for the computer-aided design of VLSI circuits.
A. Course Contents:
1. Introduction to VLSI Design and Design Automation Tools (3 hrs)
2. Algorithmic Graph Theory and Computational Complexity (3 hrs)
3. Physical Design: Partitioning , Floorplanning/Placement, Routing , Compaction (15 hrs)
4. Deep submicron electrical effects (3 hrs)
5. Logic Synthesis (9 hrs)
6. Formal Verification (3 hrs)
7. Simulation (3 hrs)
8. Testing (6 hrs)
9. High-level Synthesis (3 hrs)
10. Projects, Presentations, Exams (6 hrs) |
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課程目標 |
A. Grading:
1. Homework assignments 25%
2. Programming assignments 15%
3. One in-class test 30%.
4. Final project 30% |
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課程要求 |
B. Prerequisites
1. Logic design
2. At least one course in data structures or algorithms |
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預期每週課後學習時數 |
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Office Hours |
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指定閱讀 |
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參考書目 |
Textbook： S. H. Gerez, Algorithms for VLSI Design Automation, John Wiley & Sons, 1999. |
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評量方式
(僅供參考) |
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No. |
項目 |
百分比 |
說明 |
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1. |
Homework assignments |
25% |
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2. |
Programming assignments |
15% |
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3. |
One in-class test |
30% |
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4. |
Final project |
30% |
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